Various types of multi-patterning photolithography techniques can be utilized to manufacture semiconductor integrated circuits. Such multi-patterning techniques include sidewall image transfer (SIT), self-aligned doubled patterning (SADP), and self-aligned quadruple patterning (SAQP) techniques, for example. The current SIT, SADP and SAQP methods utilize deposition and etch back processes to create uniform memorization and transfer elements. In particular, these techniques involve spacer patterning steps in which spacers are formed on the sidewalls of sacrificial features (e.g., sacrificial mandrels), wherein the sacrificial features are removed to leave a pattern of spacers which is used to etch features into an underlying layer at sub-lithographic dimensions.
For next generation technology nodes, e.g., 10 nm and beyond, these multi-patterning methods will become costlier and more complex because of the need to fabricate and utilize multiple levels of masks (e.g., mandrel mask, block masks, cut masks, etc.) to perform such methods. The use of multiple masks adds considerable design complexity and unwanted process variations due to limitations in mask fabrication technologies. In this regard, the semiconductor industry is considering next-generation EUV lithography technologies to replace or augment such multi-patterning methods. The EUV lithography with exposure wavelengths below 40 nm would allow the semiconductor industry to print features beyond the diffraction limit of the current 193 nm lithography (ArF radiation wavelength). However, EUV lithographic patterning methods require the use of relatively thin EUV resist masks for patterning sub-36 nm pitch features to prevent resist “flop-over.” Moreover, EUV resist masks undergo more surface etching (resulting in reduction of mask thickness) as compared to ArF resist mask during drying etch processes such as reactive-ion etching (RIE).